Modern computer systems are designed with heterogeneous processing units that perform data processing operations on data values stored in memory. To access a particular data value, a processing unit implements a request address bus that designates the memory location to be accessed. Many processing units and other interconnect masters implement more request address bits than are necessary to access all the legally addressable memory locations in a system. One example of such a system comprises a processing unit with a 40 bit address bus that can address 240 bytes; a 232-byte (4 GB) addressable memory region of DRAM; and one or more small addressable memory regions, such that the sum of all addressable memory regions is significantly less than 240 bytes (1 TB).
Processing units may communicate with other processing units and memory through a transport mechanism. In such a system, addresses may be transmitted between units via buses in the transport mechanism and maybe stored in transaction tables and FIFOs in the various components. If the system contains cache coherent processing units, addresses may also be stored in cache tags. Components may perform address operations, such as decoding addresses to determine memory regions or comparing addresses to determine the result of a cache access or to detect overlapping accesses to the same memory location. Such systems store, transport, and operate on the full request address.
Storing full addresses, especially in structures such as cache tags, uses a significant amount of silicon area, which drives manufacturing cost, and transmitting full addresses requires additional wires that further increases silicon area. In addition, operating on full addresses requires significant logic gate delay that limits clock speed and system performance, and all of these artifacts increase the power consumption of the system. Therefore, what is needed is a system and method to compress addresses such as those associated with cache coherent memory locations.